Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
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LXT9763 Block Diagram .......................................................................................9
LXT9763 Pin Assignments..................................................................................10
LXT9763 Interfaces ............................................................................................17
Port Address Scheme ........................................................................................19
Management Interface Read Frame Structure ...................................................19
Management Interface Write Frame Structure ...................................................20
Interrupt Logic ....................................................................................................20
Initialization Sequence .......................................................................................22
Hardware Configuration Settings .......................................................................23
Overview of Link Establishment .........................................................................25
MII Data Interface ...............................................................................................26
Loopback Paths ..................................................................................................27
100BASE-X Frame Format ................................................................................28
100BASE-TX Data Path .....................................................................................29
Protocol Sublayers .............................................................................................30
LED Pulse Stretching .........................................................................................36
Power and Ground Supply Connections ............................................................41
Typical Twisted-Pair Interface ............................................................................42
Typical Fiber Interface ........................................................................................43
100BASE-TX Receive Timing (4B Mode) ...........................................................47
100BASE-TX Transmit Timing (4B Mode) .........................................................48
100BASE-TX Receive Timing (5B Mode) ..........................................................49
100BASE-TX Transmit Timing (5B Mode) .........................................................50
100BASE-FX Receive Timing ............................................................................51
100BASE-FX Transmit Timing ...........................................................................52
10BASE-T Receive Timing .................................................................................53
10BASE-T Transmit Timing ................................................................................54
10BASE-T SQE (Heartbeat) Timing ...................................................................54
10BASE-T Jab and Unjab Timing ......................................................................55
Auto Negotiation and Fast Link Pulse Timing ....................................................55
Fast Link Pulse Timing .......................................................................................56
MDIO Write Timing (MDIO Sourced by MAC) ....................................................56
MDIO Read Timing (MDIO Sourced by PHY) ....................................................57
Power-Up Timing ................................................................................................57
RESET And Power-Down Recovery Timing ......................................................58
PHY Identifier Bit Mapping .................................................................................64
LXT9763 Package Specification .........................................................................73
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Datasheet
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INTEL [ INTEL ]
