LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Table 38. Control Register (Address 0)
Bit
0.15
Name
Description
Type 1
Default
1 = PHY reset.
0 = Normal operation.
R/W
SC
Reset
0
0
1 = Enable loopback mode.
0 = Disable loopback mode.
0.14
0.13
Loopback
R/W
0.6
0.13
1
1
0
0
1
0
1
0
= Reserved.
Note 2
00
Speed Selection
R/W
= 1000 Mbps (not allowed).
= 100 Mbps.
= 10 Mbps.
Auto-Negotiation
Enable3
1 = Enable Auto-Negotiation Process.
0 = Disable Auto-Negotiation Process.
Note 2
0
0.12
0.11
0.10
0.9
R/W
R/W
R/W
1 = Power-down.
0 = Normal operation.
Power-Down
Isolate
0
0
0
1 = Electrically isolate PHY from MII.
0 = Normal operation.
Restart
Auto-Negotiation
1 = Restart Auto-Negotiation Process.
0 = Normal operation.
R/W
SC
1 = Full-Duplex.
0 = Half-Duplex.
Note 2
0
0.8
Duplex Mode
Collision Test
R/W
R/W
This bit is ignored by the LXT9763.
0.7
0
1 = Enable COL signal test.
0 = Disable COL signal test.
0.6
0.13
1
1
0
0
1
0
1
0
= Reserved.
= 1000 Mbps (not allowed).
= 100 Mbps.
Speed Selection
1000 Mb/s
0.6
R/W
R/W
00
= 10 Mbps.
0.5:0
Reserved
Write as 0, ignore on Read
00000
1. R/W = Read/Write.
RO = Read Only.
SC = Self Clearing when read.
2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to Table 7 on page 23).
3. Do not enable Auto-Negotiation if Fiber Mode is selected.
Table 39. Status Register (Address 1)
Bit
1.15
Name
100BASE-T4
Description
Type 1
Default
1 = PHY able to perform 100BASE-T4.
0 = PHY not able to perform 100BASE-T4.
RO
0
100BASE-X Full-
Duplex
1 = PHY able to perform full-duplex 100BASE-X.
0 = PHY not able to perform full-duplex 100BASE-X.
1.14
1.13
RO
RO
1
1
100BASE-X Half-
Duplex
1 = PHY able to perform half-duplex 100BASE-X.
0 = PHY not able to perform half-duplex 100BASE-X.
1. RO = Read Only.
LL = Latching Low.
LH = Latching High.
2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode.
62
Datasheet
INTEL [ INTEL ]
