Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
4.0
Register Definitions
The LXT9763 register set includes multiple 16-bit registers. Refer to Table 36 for a complete
register listing and to Table 37 for a complete bit map. Table 38 through Table 53 provide
additional details.
• Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 specification.
• Additional registers (16 through 30) are defined in accordance with the IEEE 802.3
specification for adding unique chip functions.
Table 36. Register Set
Address
Register Name
Bit Assignments
0
1
Control Register
Status Register
Refer to Table 38 on page 62
Refer to Table 39 on page 62
Refer to Table 40 on page 63
Refer to Table 41 on page 64
Refer to Table 42 on page 64
Refer to Table 43 on page 65
Refer to Table 44 on page 66
Refer to Table 45 on page 67
Refer to Table 46 on page 67
Not Implemented
2
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Extended Status Register
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21-27
28
29
30
31
Not Implemented
Not Implemented
Port Configuration Register
Refer to Table 47 on page 68
Refer to Table 48 on page 68
Refer to Table 49 on page 69
Refer to Table 50 on page 70
Refer to Table 51 on page 71
Quick Status Register
Interrupt Enable Register
Interrupt Status Register
LED Configuration Register
Reserved
Transmit Control Register #1
Reserved
Refer to Table 52 on page 72
Refer to Table 53 on page 72
Transmit Control Register #2
Reserved
Datasheet
59
INTEL [ INTEL ]
