LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Table 41. PHY Identification Register 2 (Address 3)
Bit
Name
Description
Type 1
Default
The PHY identifier composed of bits 19 through 24 of the
OUI.
3.15:10
PHY ID number
RO
011110
Manufacturer’s
model number
3.9:4
3.3:0
6 bits containing manufacturer’s part number.
4 bits containing manufacturer’s revision number.
RO
RO
001001
XXXX
Manufacturer’s
revision number
1. RO = Read Only.
Figure 36. PHY Identifier Bit Mapping
a
1
r
s
x
b
2
c
Organizationally Unique Identifier
18 19
24
3
0
0
1
3
9
3
I/G
0
15
0
0
1
15
0
10
4
0
0
PHY ID Register #1 (Address 2)
PHY ID Register #2 (Address 3)
0
0
0
0
1
X
X
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
X
X
X
X
0
0
0
0
0
2
B
7
5
0
3
0
00
20
7B
Manufacturer’s
Model Number
Revision
Number
The Level One OUI is 00207B hex.
Table 42. Auto Negotiation Advertisement Register (Address 4)
Bit
4.15
Name
Description
Type 1
Default
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
Next Page
Reserved
R/W
RO
0
0
0
0
0
4.14
4.13
4.12
4.11
Ignore.
1 = Remote fault.
0 = No remote fault.
Remote Fault
Reserved
R/W
R/W
R/W
Ignore.
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
4.10
Pause
R/W
0
1. R/W = Read/Write.
RO = Read Only.
2. Default value of bits 4.8:5 are determined by hardware pins at Reset. Refer to “Reset” discussion on page 22.
64
Datasheet
INTEL [ INTEL ]
