LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Figure 31. Fast Link Pulse Timing
FLP Burst
FLP Burst
TPFOP
t4
t5
Table 32. Auto Negotiation and Fast Link Pulse Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
t1
t2
t3
t4
t5
–
–
55.5
111
–
100
–
–
69.5
139
–
ns
µs
µs
ms
ms
ea
–
–
–
–
–
–
–
2
FLP burst to FLP burst
Clock/Data pulses per burst
8
–
24
17
–
33
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 32. MDIO Write Timing (MDIO Sourced by MAC)
MDC
t2
t1
MDIO
56
Datasheet
INTEL [ INTEL ]
