LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
5.2
Timing Diagrams
Figure 28. 100BASE-TX Receive Timing - 4B Mode
0ns
250ns
TPFI
t4
t5
CRS
t3
RX_DV
t1
t2
RXD<3:0>
RX_CLK
t6
t7
COL
Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
10
–
–
ns
–
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
t2
10
–
–
ns
–
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
t3
t4
t5
t6
t7
3
–
–
–
–
–
5
BT
BT
BT
BT
BT
–
–
–
–
–
12
10
16
17
16
17
22
20
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
100BASE-T bit time = 10-8 s or 10 ns.
Datasheet
61
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
