LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Tables
1
LQFP Numeric Pin List.................................................................................................... 12
2
LXT971A MII Signal Descriptions.................................................................................. 14
LXT971A Network Interface Signal Descriptions........................................................... 15
LXT971A Miscellaneous Signal Descriptions................................................................. 16
LXT971A Power Supply Signal Descriptions.................................................................. 17
LXT971A JTAG Test Signal Descriptions ...................................................................... 17
LXT971A LED Signal Descriptions ................................................................................ 17
Hardware Configuration Settings ..................................................................................... 26
Carrier Sense, Loopback, and Collision Conditions......................................................... 32
4B/5B Coding................................................................................................................... 36
BSR Mode of Operation................................................................................................... 43
Supported JTAG Instructions ........................................................................................... 43
Device ID Register ........................................................................................................... 43
Magnetics Requirements .................................................................................................. 44
I/O Pin Comparison of NIC and Switch RJ-45 Setups..................................................... 44
Absolute Maximum Ratings............................................................................................. 49
Operating Conditions........................................................................................................ 49
Digital I/O Characteristics 1............................................................................................. 50
Digital I/O Characteristics - MII Pins............................................................................... 50
I/O Characteristics - REFCLK/XI and XO Pins............................................................... 50
I/O Characteristics - LED/CFG Pins ................................................................................ 50
100BASE-TX Transceiver Characteristics....................................................................... 51
100BASE-FX Transceiver Characteristics....................................................................... 51
10BASE-T Transceiver Characteristics............................................................................ 51
10BASE-T Link Integrity Timing Characteristics ........................................................... 52
100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 53
100BASE-TX Transmit Timing Parameters - 4B Mode.................................................. 54
100BASE-FX Receive Timing Parameters ...................................................................... 55
100BASE-FX Transmit Timing Parameters..................................................................... 56
10BASE-T Receive Timing Parameters........................................................................... 57
10BASE-T Transmit Timing Parameters ......................................................................... 58
10BASE-T Jabber and Unjabber Timing Parameters....................................................... 59
10BASE-T SQE Timing Parameters ................................................................................ 59
Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 60
MDIO Timing Parameters................................................................................................ 61
Power-Up Timing Parameters .......................................................................................... 62
RESET Pulse Width and Recovery Timing Parameters.................................................. 62
Register Set....................................................................................................................... 63
Register Bit Map............................................................................................................... 64
Control Register (Address 0)............................................................................................ 66
MII Status Register #1 (Address 1) .................................................................................. 67
PHY Identification Register 1 (Address 2)....................................................................... 68
PHY Identification Register 2 (Address 3)....................................................................... 68
Auto Negotiation Advertisement Register (Address 4).................................................... 69
Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 70
Auto Negotiation Expansion (Address 6)......................................................................... 71
Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 71
Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 72
Configuration Register (Address 16, Hex 10).................................................................. 73
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
6
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
