T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
2.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line. Recovered data is output at RPOS/
RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK. Refer to Table 28
and Table 28 on page 38 for receiver timing specifications.
2.3.1
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and
timing recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411 and ITU G.823. See the “Test Specifications” section for details.
Recovered data is routed to the Loss of Signal (LOS) Monitor and through the Alarm Indication
Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled or disabled in the
receive data path or the transmit path. Received data may be routed to either the B8ZS or HDB3
decoder or neither. Finally, the device may send the digital data to the framer as either unipolar or
bipolar data.
When transmitting unipolar data to the framer, the device reports reception of bipolar violations by
driving the BPV pin High. During E1 operation, the device can report HDB3 code violations and
Zero Substitution Violations on the BPV pin.
2.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides jitter attenuation as shown in
the Test Specifications section. The JAL requires no special circuitry, such as an external quartz
crystal or high-frequency clock (higher than the line rate). Its timing reference is MCLK.
Bit CR1.JASEL0 enables or disables the JA circuit. With bit CR1.JASEL0 = 1, bit CR1.JASEL1
controls the JA circuit placement (see Table 7 on page 25). The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see Table 10 on page 26.)
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/ of a bit period. The ES produces an average
8
delay of 16 bits (or 32 bits, with the 64-bit ES option selected) in the associated data path. When
the Jitter Attenuator is in the receive path, the output RCLK transitions smoothly to MCLK in the
event of a LOS condition.
The Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store
overflow or underflow, respectively. Note that these are sticky bits that once set to 1, remain set
until the host reads the register. The ES can also provide a maskable interrupt on either overflow or
underflow.
Datasheet
15
INTEL [ INTEL ]
