T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
2.0
Functional Description
The LXT351 is a fully integrated, PCM transceiver for short-haul, 1.544 Mbps (T1) or 2.048 Mbps
(E1) applications allowing full-duplex transmission of digital data over existing twisted-pair
installations. It interfaces with two twisted-pair lines (one pair each for transmit and receive)
through standard pulse transformers and appropriate resistors.
The figure on the front page of this data sheet shows a block diagram of the LXT351. Control of
the chip is via the 8-bit parallel microprocessor port. Stand-alone operation is not supported.
The LXT351 provides a high-precision, crystal-less jitter attenuator (JA). The user may place the
JA in the transmit or receive path, or bypass it completely.
The transceiver meets or exceeds FCC, ANSI, and AT&T specifications for CSU and DSX-1
applications, as well as ITU and ETSI requirements for E1 ISDN PRI applications.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the Phase Lock
Loops (PLL). The transceiver uses a reference clock to calibrate the PLLs: the transmitter reference
is TCLK, and the receiver reference clock is MCLK. MCLK is mandatory for chip operation and
must be independent, free running, and jitter free.
2.1.1
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS and QRSS blocks.
Writing a 1 to the bit CR2.RESET commands a reset which clears all registers to 0. Allow 32 ms
for the device to settle.
2.2
Transmitter
2.2.1
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS
and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts unipolar data.
Input data may pass through either the Jitter Attenuator or B8ZS/HDB3 encoder or both. Setting
CR1.ENCENB = 1 enables B8ZS/HDB3 encoding. With zero suppression enabled, Control
Register #1 (CR1) bits EC1 through EC3 determine the coding scheme as listed in Table 8 on
page 25.
TCLK supplies input synchronization. See the Figure 14 on page 37 for the transmit timing
requirements for TCLK and the Master Clock (MCLK).
Datasheet
13
INTEL [ INTEL ]
