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LXT351QE 参数 Datasheet PDF下载

LXT351QE图片预览
型号: LXT351QE
PDF下载: 下载PDF文件 查看货源
内容描述: PCM收发器|单| CEPT PCM - 30 / E - 1 | CMOS | QFP | 44PIN |塑料\n [PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC ]
分类和应用: 电信集成电路PC
文件页数/大小: 46 页 / 1070 K
品牌: INTEL [ INTEL ]
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation LXT351  
Table 3. LXT351 Signal Descriptions (Continued)  
Pin #  
PLCC  
Symbol  
I/O1  
Description  
QFP  
Read. On an Intel bus, driving RD Low commands a LXT351 register read  
operation.  
9
7
RD / DS  
DI  
Data Strobe. On a Motorola bus, DS goes Low when data is being driven  
on the address/data bus. Data is valid on the rising edge of DS.  
Address/Data Bus 6 and 7. Used with AD0 - AD5 to form the address/  
DI/O data bus. Conforms to Intel and Motorola multiplexed address/data bus  
specifications.  
10  
11  
9
AD6  
AD7  
10  
Write. On an Intel bus, driving WR Low commands a LXT351 register write  
operation.  
12  
13  
WR / R/W  
DI  
Read/Write. On a Motorola bus, driving R/W High commands a LXT351  
register read operation; driving it Low commands a write operation.  
Transmit Tip and Ring. Differential driver output pair designed to drive a  
50 - 200 load. The transformer and line matching resistors should be  
selected to give the desired pulse height and return loss performance. See  
Application Informationon page 29.  
13  
16  
15  
19  
TTIP  
AO  
TRING  
14  
15  
16  
18  
TGND  
TVCC  
-
-
Ground return for the transmit driver power supply TVCC.  
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from  
VCC by more than ± 0.3 V.  
Chip Select. During a read or write operation, CS must remain Low. See  
Figure 16 and Figure 17 for timing requirements.  
17  
18  
20  
21  
CS  
DI  
In the case of a single processor controlling several chips, this line is used  
to select a specific transceiver.  
Interrupt. INT goes Low to flag the host when LOS, AIS, QRSS, DFMS or  
DFMO bits changes state, or when an elastic store overflow or underflow  
occurs. To identify the specific interrupt, read the Performance Status  
Register (PSR). To clear or mask an interrupt, write a one to the  
appropriate bit in the Interrupt Clear Register (ICR). To re-enable the  
interrupt, write a zero. INT is an open drain output that must be  
connected to VCC through a pull-up resistor.  
INT  
DO  
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received  
from the line is applied at these pins. A 1:1 transformer is required. Data  
and clock recovered from RTIP/RRING are output on the RPOS/RNEG (or  
RDATA in Unipolar mode), and RCLK pins.  
19  
20  
24  
25  
RTIP  
AI  
-
RRING  
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit  
drivers are supplied by TVCC.  
21  
27  
VCC  
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.  
Datasheet  
11