Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
• Eight-entry write buffer allows the core to continue execution while data is written to memory
• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with
40-bit accumulation for efficient, high-quality media and signal processing
• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle
counter for analysis of hit rates, etc.
This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of
internal bus performance.
• JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-
change messages) to debug programs
Figure 6.
Intel XScale® Core Block Diagram
Branch Target Cache
FIQ
Interrupt
Request
IRQ
M
M
U
Instruction Cache
32 KB
Instruction
South
AHB
Bus
Execution
Core
Data Cache
32 KB
Data
Address
M
M
U
Coprocessor Interface
Mini-Data Cache
2 KB
Data
Multiply
Accumulate
System
Management
Debug/
PMU
JTAG
A9568-02
2.2.1
Super Pipeline
The super pipeline is composed of integer, multiply-accumulate (MAC), and memory pipes.
The integer pipe has seven stages:
• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute
• Integer Writeback
Datasheet
March 2005
27
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
