Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
2.1.4
UTOPIA 2
The integrated, UTOPIA-2 interface works with a network processing engine, for several of the
IXP42X product line and IXC1100 control plane processors. (See Table 4 on page 20.)
The UTOPIA-2 interface supports a single- or a multiple-physical-interface configuration with
cell-level or octet-level handshaking. The network processing engine handles segmentation and
reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory. This
allows parallel processing of data traffic on the UTOPIA-2 interface, off-loading processor
overhead required by the Intel XScale® Core.
The IXP42X product line and IXC1100 control plane processors are compliant with the ATM
Forum, UTOPIA Level-2 Specification, Revision 1.0.
2.1.5
USB Interface
The integrated USB 1.1 interface is a device-only controller. The interface supports full-speed
operation and 16 endpoints and includes an integrated transceiver.
There are:
• Six isochronous endpoints (three input and three output)
• One control endpoints
• Three interrupt endpoints
• Six bulk endpoints (three input and three output)
2.1.6
2.1.7
PCI Controller
The IXP42X product line and IXC1100 control plane processors’ PCI controller is compatible with
the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable
of operating as either a host or an option (i.e., not the Host) For more information on PCI
Controller support and configuration see the Intel® IXP42X Product Line of Network Processors
and IXC1100 Control Plane Processor Developer’s Manual.
SDRAM Controller
The memory controller manages the interface to external SDRAM memory chips. The interface:
• Operates at 133.32 MHz (which is 4 * OSC_IN input pin.)
• Supports eight open pages simultaneously
• Has two banks to support memory configurations from 8 Mbyte to 256 Mbyte
The memory controller only supports 32-bit memory. If a x16 memory chip is used, a minimum of
two memory chips would be required to facilitate the 32-bit interface required by the IXP42X
product line and IXC1100 control plane processors. A maximum of four SDRAM memory chips
may be attached to the processors. For more information on SDRAM support and configuration see
the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
The memory controller internally interfaces to the North AHB and South AHB with independent
interfaces. This architecture allows SDRAM transfers to be interleaved and pipelined to achieve
maximum possible efficiency.
Datasheet
March 2005
Document Number: 252479, Revision: 005
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