Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Once the AHB/AHB bridge has obtained the read information from the peripheral on the South
AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has
the data for the master that requested the “split” transfer. The master on the North AHB — that
requested the split transfer — will arbitrate for the North AHB and transfer the read data from the
AHB/AHB bridge. The North AHB is released to complete another transaction while the North
AHB master — that requested the “split” transfer — waits for the data to arrive.
These “posting” and “splitting” transfers allow control of the North AHB to be given to another
master on the North AHB — enabling the North AHB to achieve maximum efficiency. Transfers to
the AHB/AHB bridge are considered to be small and infrequent, relative to the traffic passed
between the NPEs on the North AHB and the SDRAM.
2.1.2.2
2.1.2.3
South AHB
The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale® Core, PCI
controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI
interface, queue manager, expansion bus, or the APB/AHB bridge.
Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the APB.
APB Bus
The APB Bus is a 66.66 MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be mastered by
the AHB/APB bridge only. The targets of the APB bus can be:
• High-speed UART interface
• USB v1.1 interface
• Console UART interface
• All NPEs
• Internal bus performance monitoring unit
(IBPMU)
• Interrupt controller
• GPIO
• Timers
The APB interface is also used as an alternate-path interface to the NPEs and is used for NPE code
download and configuration.
2.1.3
MII Interfaces
Two industry-standard, media-independent interface (MII) interfaces are integrated into most of
the IXP42X product line and IXC1100 control plane processors with separate media-access
controllers and independent network processing engines. (See Table 4 on page 20.)
The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces
and off-loading of processing required by the Intel XScale® Core. The IXP42X product line and
IXC1100 control plane processors are compliant with the IEEE, 802.3 specification.
In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane processors
include a single management data interface that is used to configure and control PHY devices that
are connected to the MII interface.
March 2005
22
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
