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EPM7512AEQC208-7 参数 Datasheet PDF下载

EPM7512AEQC208-7图片预览
型号: EPM7512AEQC208-7
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 66 页 / 1120 K
品牌: INTEL [ INTEL ]
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MAX 7000A Programmable Logic Device Data Sheet  
Notes to tables:  
(1) See the Operating Requirements for Altera Devices Data Sheet.  
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents  
less than 100 mA and periods shorter than 20 ns.  
(3) For EPM7128A and EPM7256A devices only, V must rise monotonically.  
CC  
(4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before  
V
and V  
are powered.  
CCINT  
CCIO  
(5) These devices support in-system programming for –40° to 100° C. For in-system programming support between  
–40° and 0° C, contact Altera Applications.  
(6) These values are specified under the recommended operating conditions shown in Table 11 on page 24.  
(7) The parameter is measured with 50% of the outputs each sourcing the specified current. The I  
parameter refers  
OH  
to high-level TTL or CMOS output current.  
(8) The parameter is measured with 50% of the outputs each sinking the specified current. The I parameter refers to  
OL  
low-level TTL or CMOS output current.  
(9) This value is specified for normal device operation. For MAX 7000AE devices, the maximum leakage current during  
power-up is 300 µA. For EPM7128A and EPM7256A devices, leakage current during power-up is not specified.  
(10) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system.  
(11) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed  
devices during power-up.  
(12) Capacitance is measured at 25 °C and is sample-tested only. The OE1pin (high-voltage pin during programming)  
has a maximum capacitance of 20 pF.  
(13) The POR time for MAX 7000AE devices (except MAX 7128A and MAX 7256A devices) does not exceed 100 µs. The  
sufficient V  
voltage level for POR is 3.0 V. The device is fully initialized within the POR time after V  
CCINT  
CCINT  
reaches the sufficient POR voltage level.  
26  
Altera Corporation  
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