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EPM7512AEQC208-7 参数 Datasheet PDF下载

EPM7512AEQC208-7图片预览
型号: EPM7512AEQC208-7
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 66 页 / 1120 K
品牌: INTEL [ INTEL ]
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MAX 7000A Programmable Logic Device Data Sheet  
Because MAX 7000A devices can be used in a mixed-voltage environment,  
they have been designed specifically to tolerate any possible power-up  
sequence. The VCCIO and VCCINT power planes can be powered in any  
order.  
Power  
Sequencing &  
Hot-Socketing  
Signals can be driven into MAX 7000AE devices before and during power-  
up (and power-down) without damaging the device. Additionally,  
MAX 7000AE devices do not drive out during power-up. Once operating  
conditions are reached, MAX 7000AE devices operate as specified by the  
user.  
All MAX 7000A devices contain a programmable security bit that controls  
access to the data programmed into the device. When this bit is  
programmed, a design implemented in the device cannot be copied or  
retrieved. This feature provides a high level of design security because  
programmed data within EEPROM cells is invisible. The security bit that  
controls this function, as well as all other programmed data, is reset only  
when the device is reprogrammed.  
Design Security  
Generic Testing  
MAX 7000A devices are fully tested. Complete testing of each  
programmable EEPROM bit and all internal logic elements ensures 100%  
programming yield. AC test measurements are taken under conditions  
equivalent to those shown in Figure 9. Test patterns can be used and then  
erased during early stages of the production flow.  
Figure 9. MAX 7000A AC Test Conditions  
Power supply transients can affect AC  
measurements. Simultaneous transitions  
of multiple outputs should be avoided for  
accurate measurement. Threshold tests  
must not be performed under AC  
conditions. Large-amplitude, fast-ground-  
current transients normally occur as the  
device outputs discharge the load  
VCC  
703 Ω  
[521 ]  
Device  
Output  
To Test  
System  
capacitances. When these transients flow  
through the parasitic inductance between  
the device ground pin and the test system  
ground, significant reductions in  
observable noise immunity can result.  
Numbers in brackets are for 2.5-V  
outputs. Numbers without brackets are for  
3.3-V outputs.  
586 Ω  
[481 ]  
C1 (includes jig  
capacitance)  
Device input  
rise and fall  
times < 2 ns  
Altera Corporation  
23  
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