MAX 3000A Programmable Logic Device Family Data Sheet
Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–4
–10
Min
Max Min
Max
Min
Max
tCLR
tPIA
Register clear time
PIA delay
1.3
1.0
3.5
2.1
1.7
4.0
2.9
2.3
5.0
ns
ns
ns
(2)
(5)
tLPA
Low–power adder
Table 20. EPM3128A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–5
–10
Min
Max
Min
Max
Min
Max
tPD1
tPD2
tSU
Input to non–
registered output
C1 = 35 pF
(2)
5.0
7.5
10
ns
ns
ns
I/O input to non–
registered output
C1 = 35 pF
(2)
5.0
7.5
5.0
10
Global clock setup
time
(2)
3.3
4.9
6.6
tH
Global clock hold time (2)
0.0
1.0
0.0
1.0
0.0
1.0
ns
ns
tCO1
Global clock to output C1 = 35 pF
delay
3.4
6.6
tCH
Global clock high time
2.0
2.0
1.8
0.2
1.0
3.0
3.0
2.8
0.3
1.0
4.0
4.0
3.8
0.4
1.0
ns
ns
ns
ns
ns
tCL
Global clock low time
tASU
tAH
Array clock setup time (2)
Array clock hold time (2)
Array clock to output C1 = 35 pF
tACO1
4.9
7.1
9.4
delay
(2)
tACH
tACL
Array clock high time
Array clock low time
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
ns
ns
ns
tCPPW
Minimum pulse width (3)
for clear and preset
tCNT
fCNT
tACNT
Minimum global clock (2)
period
5.2
5.2
7.7
7.7
10.2
10.2
ns
MHz
ns
Maximum internal
(2), (4)
192.3
129.9
98.0
global clock frequency
Minimum array clock (2)
period
32
Altera Corporation
INTEL [ INTEL ]
