MAX 3000A Programmable Logic Device Family Data Sheet
Table 17. EPM3032A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–4
–10
Min
Max Min
Max
Min
Max
tPIA
PIA delay
Low–power adder
(2)
(5)
0.9
2.5
1.5
4.0
2.1
5.0
ns
ns
tLPA
Table 18. EPM3064A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–4
–10
Min
Max
Min
Max
Min
Max
tPD1
tPD2
Input to non–registered
output
C1 = 35 pF (2)
4.5
7.5
10.0
ns
ns
I/O input to non–registered C1 = 35 pF (2)
4.5
7.5
10.0
output
tSU
Global clock setup time
Global clock hold time
(2)
(2)
2.8
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
4.7
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
3.0
6.2
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tCO1
tCH
Global clock to output delay C1 = 35 pF
Global clock high time
3.1
5.1
7.0
tCL
Global clock low time
tASU
tAH
Array clock setup time
Array clock hold time
(2)
(2)
tACO1
tACH
tACL
tCPPW
Array clock to output delay C1 = 35 pF (2)
Array clock high time
4.3
7.2
9.6
Array clock low time
Minimum pulse width for
clear and preset
(3)
tCNT
fCNT
Minimum global clock
period
(2)
4.5
4.5
7.4
7.4
10.0
10.0
ns
Maximum internal global
clock frequency
(2), (4)
222.2
222.2
135.1
135.1
100.0
100.0
MHz
tACNT
fACNT
Minimum array clock period (2)
ns
Maximum internal array
clock frequency
(2), (4)
MHz
30
Altera Corporation
INTEL [ INTEL ]
