MAX 3000A Programmable Logic Device Family Data Sheet
Tables 16 through 23 show EPM3032A, EPM3064A, EPM3128A,
EPM3256A, and EPM3512A timing information.
Table 16. EPM3032A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–4
–10
Min
Max
Min
Max
Min
Max
tPD1
tPD2
tSU
Input to non–
registered output
C1 = 35 pF
(2)
4.5
7.5
10
ns
ns
ns
I/O input to non–
registered output
C1 = 35 pF
(2)
4.5
7.5
5.0
10
Global clock setup
time
(2)
2.9
4.7
6.3
tH
Global clock hold time (2)
0.0
1.0
0.0
1.0
0.0
1.0
ns
ns
tCO1
Global clock to output C1 = 35 pF
delay
3.0
6.7
tCH
Global clock high time
2.0
2.0
1.6
0.3
1.0
3.0
3.0
2.5
0.5
1.0
4.0
4.0
3.6
0.5
1.0
ns
ns
ns
ns
ns
tCL
Global clock low time
tASU
tAH
Array clock setup time (2)
Array clock hold time (2)
Array clock to output C1 = 35 pF
tACO1
4.3
7.2
9.4
delay
(2)
tACH
tACL
Array clock high time
Array clock low time
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
ns
ns
ns
tCPPW
Minimum pulse width (3)
for clear and preset
tCNT
Minimum global clock (2)
period
4.4
4.4
7.2
7.2
9.7
9.7
ns
MHz
ns
fCNT
Maximum internal
(2), (4)
227.3
227.3
138.9
138.9
103.1
103.1
global clock frequency
tACNT
fACNT
Minimum array clock (2)
period
Maximum internal
(2), (4)
MHz
array clock frequency
28
Altera Corporation
INTEL [ INTEL ]
