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EPM570T144C5N 参数 Datasheet PDF下载

EPM570T144C5N图片预览
型号: EPM570T144C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.7ns, 440-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
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Chapter 5: DC and Switching Characteristics  
5–21  
Timing Model and Specifications  
Table 5–26 shows the external I/O timing parameters for EPM2210 devices.  
Table 5–26. EPM2210 Global Clock External I/O Timing Parameters  
MAX II / MAX IIG  
–3 Speed Grade –4 Speed Grade –5 Speed Grade  
Symbol  
tPD1  
Parameter  
Condition  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Worst case pin-to-pin delay  
through 1 look-up table  
(LUT)  
10 pF  
7.0  
9.1  
11.2  
ns  
tPD2  
Best case pin-to-pin delay  
through 1 LUT  
10 pF  
3.7  
4.8  
5.9  
ns  
tSU  
tH  
Global clock setup time  
Global clock hold time  
Global clock to output delay  
Global clock high time  
Global clock low time  
1.2  
0
4.6  
1.5  
0
6.0  
1.9  
0
7.4  
ns  
ns  
ns  
ps  
ps  
ns  
tCO  
tCH  
tCL  
tCNT  
10 pF  
2.0  
166  
166  
3.3  
2.0  
216  
216  
4.0  
2.0  
266  
266  
5.0  
Minimum global clock  
period for  
16-bit counter  
fCNT  
Maximum global clock  
frequency for 16-bit counter  
304.0  
(1)  
247.5  
201.1  
MHz  
Note to Table 5–26:  
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global  
clock input pin maximum frequency.  
External Timing I/O Delay Adders  
The I/O delay timing parameters for I/O standard input and output adders, and  
input delays are specified by speed grade independent of device density.  
Table 5–27 through Table 5–31 show the adder delays associated with I/O pins for all  
packages. The delay numbers for –3, –4, and –5 speed grades shown in Table 5–27  
through Table 5–33 are based on an EPM1270 device target, while –6, –7, and –8 speed  
grade values are based on an EPM570Z device target. If an I/O standard other than  
3.3-V LVTTL is selected, add the input delay adder to the external tSU timing  
parameters shown in Table 5–23 through Table 5–26. If an I/O standard other than  
3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output  
delay adder to the external tCO and tPD shown in Table 5–23 through Table 5–26.  
Table 5–27. External Timing Input Delay Adders (Part 1 of 2)  
MAX II / MAX IIG  
MAX IIZ  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
–8 Speed  
Grade  
I/O Standard  
3.3-V LVTTL Without Schmitt  
Min Max Min Max Min Max Min Max Min Max Min Max Unit  
0
0
0
0
0
0
ps  
Trigger  
With Schmitt  
Trigger  
334  
434  
535  
387  
434  
442  
ps  
© August 2009 Altera Corporation  
MAX II Device Handbook