Chapter 5: DC and Switching Characteristics
5–19
Timing Model and Specifications
Table 5–23. EPM240 Global Clock External I/O Timing Parameters (Part 2 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit
fCNT
Maximum
global clock
frequencyfor
16-bit
—
—
304.0
(1)
—
247.5
—
201.1
—
184.1
—
123.5
—
118.3 MHz
counter
Note to Table 5–23:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock
input pin maximum frequency.
Table 5–24 shows the external I/O timing parameters for EPM570 devices.
Table 5–24. EPM570 Global Clock External I/O Timing Parameters (Part 1 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol
Parameter
Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit
tPD1
Worst case pin-
to-pin delay
10 pF
—
5.4
—
7.0
—
8.7
—
9.5
—
15.1
—
17.7
ns
through 1 look-
up table (LUT)
tPD2
Best case pin-
to-pin delay
10 pF
—
3.7
—
4.8
—
5.9
—
5.7
—
7.7
—
8.5
ns
through 1 LUT
tSU
tH
Global clock
setup time
—
—
1.2
0
—
—
4.5
—
—
—
1.5
0
—
—
5.8
—
—
—
1.9
0
—
—
7.1
—
—
—
2.2
0
—
—
6.7
—
—
—
3.9
0
—
—
8.2
—
—
—
4.4
0
—
—
8.7
—
—
—
ns
ns
ns
ps
ps
ns
Global clock
hold time
tCO
tCH
tCL
tCNT
Global clock to
output delay
10 pF
—
2.0
166
166
3.3
2.0
216
216
4.0
2.0
266
266
5.0
2.0
253
253
5.4
2.0
335
335
8.1
2.0
339
339
8.4
Global clock
high time
Global clock
low time
—
Minimum
—
global clock
period for
16-bit counter
© August 2009 Altera Corporation
MAX II Device Handbook
INTEL [ INTEL ]
