5–18
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in Table 5–27 through Table 5–31.
f
For more information about each external timing parameters symbol, refer to the
Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook.
Table 5–23 shows the external I/O timing parameters for EPM240 devices.
Table 5–23. EPM240 Global Clock External I/O Timing Parameters (Part 1 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit
tPD1
Worst case
pin-to-pin
delay
10 pF
—
4.7
—
6.1
—
7.5
—
7.9
—
12.0
—
14.0
ns
through 1
look-up table
(LUT)
tPD2
Best case
pin-to-pin
delay
10 pF
—
3.7
—
4.8
—
5.9
—
5.8
—
7.8
—
8.5
ns
through
1 LUT
tSU
tH
Global clock
setup time
—
—
1.7
0
—
—
2.2
0
—
—
2.7
0
—
—
2.4
0
—
—
4.1
0
—
—
4.6
0
—
—
ns
ns
ns
Global clock
hold time
tCO
Global clock
to output
delay
10 pF
2.0
4.3
2.0
5.6
2.0
6.9
2.0
6.6
2.0
8.1
2.0
8.6
tCH
tCL
Global clock
high time
—
—
—
166
166
3.3
—
—
—
216
216
4.0
—
—
—
266
266
5.0
—
—
—
253
253
5.4
—
—
—
335
335
8.1
—
—
—
339
339
8.4
—
—
—
ps
ps
ns
Global clock
low time
tCNT
Minimum
global clock
period for
16-bit
counter
MAX II Device Handbook
© August 2009 Altera Corporation
INTEL [ INTEL ]
