Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
4–7
Figure 4–5.
Power-Up Characteristics for MAX II, MAX IIG, and MAX IIZ Devices
V
CCINT
3.3 V
2.5 V
Device Resets
the
SRAM
and
Tri-States I/O Pins
MAX II Device
Approximate Voltage
for
SRAM
Download
Start
1.7 V
1.4 V
t
CONFIG
0V
Tri-State
User Mode
Operation
Tri-State
V
CCINT
3.3 V
MAX IIG Device
Approximate Voltage
for
SRAM
Download
Start
1.8 V
1.55 V
1.4 V
t
CONFIG
0V
Tri-State
User Mode
Operation
Device Resets
the
SRAM
and
Tri-States I/O Pins
Tri-State
V
CCINT
3.3 V
MAX IIZ Device
Approximate Voltage
for
SRAM
Download
Start
1.8 V
1.55 V
1.4 V
t
CONFIG
0V
Tri-State
User Mode
Operation
V
CCINT
must be powered down
to 0 V if the V
CCINT
dips below this level
minimum 10
µs
t
CONFIG
User Mode
Operation
Tri-State
Notes to
(1) Time scale is relative.
(2)
assumes all V
CCIO
banks power up simultaneously with the V
CCINT
profile shown. If not, t
CONFIG
stretches out until all V
CCIO
banks are powered.
1
After SRAM configuration, all registers in the device are cleared and released into
user function before I/O tri-states are released. To release clears after tri-states are
released, use the
DEV_CLRn
pin option. To hold the tri-states beyond the power-up
configuration time, use the
DEV_OE
pin option.
INTEL [ INTEL CORPORATION ]
