Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
4–5
When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V
is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current
path is from GND to the I/O pin, as shown in
Figure 4–4.
ESD Protection During Negative Voltage Zap
I/O
Source
PMOS
Gate
N+
D
Drain
I/O
Drain
P-Substrate
G
NMOS
Gate
N+
S
Source
GND
GND
Power-On Reset Circuitry
MAX II devices have POR circuits to monitor V
CCINT
and V
CCIO
voltage levels during
power-up. The POR circuit monitors these voltages, triggering download from the
non-volatile configuration flash memory (CFM) block to the SRAM logic, maintaining
tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this
process. When the MAX II device enters user mode, the POR circuit releases the I/O
pins to user functionality. The POR circuit of the MAX II (except MAX IIZ) device
continues to monitor the V
CCINT
voltage level to detect a brown-out condition. The
POR circuit of the MAX IIZ device does not monitor the V
CCINT
voltage level after the
device enters into user mode. More details are provided in the following sub-sections.
INTEL [ INTEL CORPORATION ]
