欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM570F256C5N 参数 Datasheet PDF下载

EPM570F256C5N图片预览
型号: EPM570F256C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.7ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
 浏览型号EPM570F256C5N的Datasheet PDF文件第80页浏览型号EPM570F256C5N的Datasheet PDF文件第81页浏览型号EPM570F256C5N的Datasheet PDF文件第82页浏览型号EPM570F256C5N的Datasheet PDF文件第83页浏览型号EPM570F256C5N的Datasheet PDF文件第84页浏览型号EPM570F256C5N的Datasheet PDF文件第86页浏览型号EPM570F256C5N的Datasheet PDF文件第87页浏览型号EPM570F256C5N的Datasheet PDF文件第88页  
Chapter 5: DC and Switching Characteristics  
5–27  
Document Revision History  
Document Revision History  
Table 5–35 shows the revision history for this chapter.  
Table 5–35. Document Revision History (Part 1 of 2)  
Date and Revision  
Changes Made  
Summary of Changes  
August 2009,  
version 2.5  
Added Table 5–28, Table 5–29, and Table 5–30.  
Added information for  
speed grade –8  
Updated Table 5–2, Table 5–4, Table 5–14, Table 5–15, Table 5–16,  
Table 5–17, Table 5–18, Table 5–19, Table 5–20, Table 5–21,  
Table 5–22, Table 5–23, Table 5–24, Table 5–27, Table 5–31,  
Table 5–32, and Table 5–33.  
November 2008,  
version 2.4  
Updated Table 5–2.  
Updated “Internal Timing Parameters” section.  
Updated New Document Format.  
UpdatedFigure 5–1.  
October 2008,  
version 2.3  
July 2008,  
version 2.2  
Updated Table 5–14 , Table 5–23 , and Table 5–24.  
March 2008,  
version 2.1  
Added (Note 5) to Table 5–4.  
December 2007,  
version 2.0  
Updated (Note 3) and (4) to Table 5–1.  
Updated Table 5–2 and added (Note 5).  
Updated document with  
MAX IIZ information.  
Updated ICCSTANDBY and ICCPOWERUP information and added  
IPULLUP information in Table 5–4.  
Added (Note 1) to Table 5–10.  
Updated Figure 5–2.  
Added (Note 1) to Table 5–13.  
Updated Table 5–13 through Table 5–24, and Table 5–27 through  
Table 5–30.  
Added tCOMB information to Table 5–15.  
Updated Figure 5–6.  
Added “Referenced Documents” section.  
Added note to Table 5–1.  
December 2006,  
version 1.8  
Added document revision history.  
Minor content and table updates.  
July 2006,  
version 1.7  
February 2006,  
version 1.6  
Updated “External Timing I/O Delay Adders” section.  
Updated Table 5–29.  
Updated Table 5–30.  
November 2005,  
version 1.5  
Updated Tables 5-2, 5-4, and 5-12.  
August 2005,  
version 1.4  
Updated Figure 5-1.  
Updated Tables 5-13, 5-16, and 5-26.  
Removed Note 1 from Table 5-12.  
© August 2009 Altera Corporation  
MAX II Device Handbook