Chapter 5: DC and Switching Characteristics
5–15
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tDDS
Data register data in
setup to data register
clock
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
—
ns
ns
ns
tDDH
Data register data in
hold from data
register clock
tDP
tPB
Program signal to
data clock hold time
0
—
0
—
0
—
0
—
0
—
0
Maximum delay
between program
rising edge to UFM
busy signal rising
edge
—
960
—
960
—
960
—
960
—
960
—
960 ns
tBP
Minimum delay
allowed from UFM
busy signal going low
to program signal
going low
20
—
20
—
20
—
20
—
20
—
20
—
ns
tPPMX
Maximum length of
busy pulse during a
program
—
0
100
—
—
0
100
—
—
0
100
—
—
0
100
—
—
0
100
—
—
0
100 µs
tAE
Minimum erase signal
to address clock hold
time
—
ns
tEB
Maximum delay
between the erase
rising edge to the
UFM busy signal
rising edge
—
960
—
960
—
960
—
960
—
960
—
960 ns
tBE
Minimum delay
allowed from the UFM
busy signal going low
to erase signal going
low
20
—
20
—
20
—
20
—
20
—
20
—
ns
tEPMX
Maximum length of
busy pulse during an
erase
—
—
500
5
—
—
500
5
—
—
500
5
—
—
500
5
—
—
500
5
—
—
500 ms
tDCO
Delay from data
register clock to data
register output
5
ns
© August 2009 Altera Corporation
MAX II Device Handbook
INTEL [ INTEL ]
