5–12
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–16. IOE Internal Timing Microparameters
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tFASTIO
Data output delay
from adjacent LE
to I/O block
—
159
—
207
—
254
—
170
—
348
—
428
ps
tIN
I/O input pad and
buffer delay
—
—
708
—
—
920
—
—
1,132
2,430
—
—
907
—
—
970
—
—
986
ps
ps
tGLOB (1) I/O input pad and
1,519
1,974
2,261
2,670
3,322
buffer delay used
as global signal pin
tIOE
Internally
generated output
enable delay
—
354
—
374
—
460
—
530
—
966
—
1,410 ps
tDL
Input routing delay
—
—
224
—
—
291
—
—
358
—
—
318
—
—
410
—
—
509
ps
ps
tOD (2)
Output delay buffer
and pad delay
1,064
1,383
1,702
1,319
1,526
1,543
tXZ (3)
tZX (4)
Output buffer
disable delay
—
—
756
—
—
982
—
—
1,209
1,604
—
—
1,045
1,160
—
—
1,264
1,325
—
—
1,276
1,353
ps
ps
Output buffer
enable delay
1,003
1,303
Notes to Table 5–16:
(1) Delay numbers for tGLOB differ for each device density and speed grade. The delay numbers for tGLOB, shown in Table 5–16, are based on an EPM240
device target.
(2) Refer to Table 5–32 and 5–24 for delay adders associated with different I/O standards, drive strengths, and slew rates.
(3) Refer to Table 5–19 and 5–14 for tXZ delay adders associated with different I/O standards, drive strengths, and slew rates.
(4) Refer to Table 5–17 and 5–13 for tZX delay adders associated with different I/O standards, drive strengths, and slew rates.
Table 5–17 through Table 5–20 show the adder delays for tZX and tXZ microparameters
when using an I/O standard other than 3.3-V LVTTL with 16 mA drive strength.
Table 5–17. tZX IOE Microparameter Adders for Fast Slew Rate
(Part 1 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Standard
3.3-V LVTTL
Min
—
—
—
—
—
—
—
—
Max Min Max Min
Max
0
Min Max Min Max Min Max
Unit
ps
ps
ps
ps
ps
ps
ps
ps
16 mA
8 mA
0
28
—
—
—
—
—
—
—
—
0
37
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
0
45
72
71
74
3.3-V LVCMOS 8 mA
4 mA
0
0
0
0
0
0
28
37
45
72
71
74
2.5-V LVTTL / 14 mA
LVCMOS
14
19
23
75
87
90
7 mA
314
450
1,443
409
585
1,876
503
720
2,309
162
279
499
174
289
508
177
291
512
1.8-V LVTTL /
LVCMOS
6 mA
3 mA
MAX II Device Handbook
© August 2009 Altera Corporation
INTEL [ INTEL ]
