Chapter 5: DC and Switching Characteristics
5–17
Timing Model and Specifications
Figure 5–4. UFM Program Waveforms
9 Address Bits
tACLK
ARShft
ARClk
tAH
tASU
tADH
ARDin
DRShft
DRClk
DRDin
DRDout
tADS
16 Data Bits
tDCLK
tDSH
tDSS
tDDH
tDDS
tOSCH
tOSCS
OSC_ENA
Program
tPB
Erase
Busy
tBP
tPPMX
Figure 5–5. UFM Erase Waveform
ARShft
9 Address Bits
tACLK
tAH
tADH
tASU
ARClk
ARDin
DRShft
DRClk
DRDin
DRDout
tADS
OSC_ENA
tOSCS
tEB
tOSCH
Program
Erase
tBE
Busy
tEPMX
Table 5–22. Routing Delay Internal Timing Microparameters
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Routing
Min
Max
429
326
330
Min
Max
556
423
429
Min
Max
687
521
529
Min
Max
(1)
Min
Max
(1)
Min
Max
Unit
ps
tC4
tR4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
ps
tLOCAL
(1)
(1)
ps
Note to Table 5–22:
(1) The numbers will only be available in a later revision.
© August 2009 Altera Corporation
MAX II Device Handbook
INTEL [ INTEL ]
