5–10
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–13. MAX II Device Timing Model Status (Part 2 of 2)
Device
EPM1270
Preliminary
Final
v
—
—
EPM2210
v
Note to Table 5–13:
(1) The MAX IIZ device timing models are only available in the Quartus II software
version 8.0 and later.
Performance
Table 5–14 shows the MAX II device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions. Performance values for –3, –4, and –5 speed grades are based on an
EPM1270 device target, while –6, –7, and –8 speed grades are based on an EPM570Z
device target.
Table 5–14. MAX II Device Performance
Performance
MAX II / MAX IIG
–3 –4 –5
Resources Used
MAX IIZ
–7
–6
–8
Resource
Used
Design Size and
Function
UFM
Speed Speed Speed Speed Speed Speed
Mode
—
LEs Blocks Grade Grade Grade Grade Grade Grade Unit
LE
16-bit counter (1)
64-bit counter (1)
16-to-1 multiplexer
32-to-1 multiplexer
16-bit XOR function
16
64
11
24
5
0
0
0
0
0
0
304.0 247.5 201.1 184.1 123.5 118.3 MHz
—
201.5 154.8 125.8
83.2
17.4
12.5
9.0
83.2
17.3
22.8
15.0
15.0
80.5 MHz
—
6.0
7.1
5.1
5.2
8.0
9.0
6.6
6.6
9.3
11.4
8.2
20.4
25.3
16.1
16.1
ns
ns
ns
ns
—
—
16-bit decoder with
single address line
—
5
8.2
9.2
UFM
512 × 16
512 × 16
512 × 8
None
3
1
1
1
10.0
8.0
10.0
8.0
(4)
10.0
8.0
10.0
9.7
10.0
9.7
(4)
10.0 MHz
SPI (2)
37
73
9.7
MHz
MHz
Parallel
(4)
(4)
(4)
(4)
(3)
2
512 × 16
I C (3) 142
1
100
100
100
100
100
100
kHz
(5)
(5)
(5)
(5)
(5)
(5)
Notes to Table 5–14:
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of LEs used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I2C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
MAX II Device Handbook
© August 2009 Altera Corporation
INTEL [ INTEL ]
