MAX II Architecture
The bus-hold circuitry uses a resistor to pull the signal level to the last
driven state. The chapter on DC & Switching Characteristics gives the
specific sustaining current for each VCCIO voltage level driven through
this resistor and overdrive current used to identify the next-driven input
level.
The bus-hold circuitry is only active after the device has fully initialized.
The bus-hold circuit captures the value on the pin present at the moment
user mode is entered.
Programmable Pull-Up Resistor
Each MAX II device I/O pin provides an optional programmable pull-up
resistor during user mode. If the designer enables this feature for an I/O
pin, the pull-up resistor holds the output to the VCCIO level of the output
pin’s bank.
1
The programmable pull-up resistor feature should not be used
at the same time as the bus-hold feature on a given I/O pin.
Programmable Input Delay
The MAX II IOE includes a programmable input delay that is activated to
ensure zero hold times. A path where a pin directly drives a register, with
minimal routing between the two, may require the delay to ensure zero
hold time. However, a path where a pin drives a register through long
routing or through combinational logic may not require the delay to
achieve a zero hold time. The Quartus II software uses this delay to
ensure zero hold times when needed.
MultiVolt I/O Interface
The MAX II architecture supports the MultiVolt I/O interface feature,
which allows MAX II devices in all packages to interface with systems of
different supply voltages. The devices have one set of VCCpins for
internal operation (VCCINT), and four sets for input buffers and I/O
output driver buffers (VCCIO).
Altera Corporation
August 2006
Core Version a.b.c variable
2–39
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
