Chapter 3. JTAG & In-System
Programmability
MII51003-1.3
All MAX® II devices provide Joint Test Action Group (JTAG) boundary-
scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001
specification. JTAG boundary-scan testing can only be performed at any
time after VCCINT and all VCCIO banks have been fully powered and a
IEEE Std. 1149.1
(JTAG)Boundary
Scan Support
t
CONFIG amount of time has passed. MAX II devices can also use the JTAG
®
port for in-system programming together with either the Quartus II
TM
software or hardware using Programming Object Files (.pof), Jam
Standard Test and Programming Language (STAPL) Files (.jam) or Jam
Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard is determined by the VCCIO of the
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in Table 3–1.
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
EXTEST(1)
00 0000 1111
11 1111 1111
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDIand TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation.
USERCODE
IDCODE
00 0000 0111
00 0000 0110
Selects the 32-bit USERCODEregister and places it between
the TDIand TDOpins, allowing the USERCODEto be serially
shifted out of TDO. This register defaults to all 1’s if not
specified in the Quartus II software.
Selects the IDCODEregister and places it between TDIand
TDO, allowing the IDCODE to be serially shifted out of TDO.
Altera Corporation
June 2005
Core Version a.b.c variable
3–1
Preliminary
INTEL [ INTEL ]
