欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM1270GF100I4N 参数 Datasheet PDF下载

EPM1270GF100I4N图片预览
型号: EPM1270GF100I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL ]
 浏览型号EPM1270GF100I4N的Datasheet PDF文件第29页浏览型号EPM1270GF100I4N的Datasheet PDF文件第30页浏览型号EPM1270GF100I4N的Datasheet PDF文件第31页浏览型号EPM1270GF100I4N的Datasheet PDF文件第32页浏览型号EPM1270GF100I4N的Datasheet PDF文件第34页浏览型号EPM1270GF100I4N的Datasheet PDF文件第35页浏览型号EPM1270GF100I4N的Datasheet PDF文件第36页浏览型号EPM1270GF100I4N的Datasheet PDF文件第37页  
MAX II Architecture  
MAX II devices feature a single UFM block, which can be used like a serial  
EEPROM for storing non-volatile information up to 8,192 bits. The UFM  
block connects to the logic array through the MultiTrack interconnect,  
allowing any LE to interface to the UFM block. Figure 2–15 shows the  
UFM block and interface signals. The logic array is used to create  
customer interface or protocol logic to interface the UFM block data  
outside of the device. The UFM block offers the following features:  
User Flash  
Memory Block  
Non-volatile storage up to 16-bit wide and 8,192 total bits  
Two sectors for partitioned sector erase  
Built-in internal oscillator that optionally drives logic array  
Program, erase, and busy signals  
Auto-increment addressing  
Serial interface to logic array with programmable interface  
Figure 2–15. UFM Block & Interface Signals  
UFM Block  
PROGRAM  
ERASE  
RTP_BUSY  
BUSY  
Program  
Erase  
Control  
_
:
OSC  
4
OSC_ENA  
OSC  
UFM Sector 1  
UFM Sector 0  
9
ARCLK  
Address  
Register  
16  
16  
ARSHFT  
ARDin  
DRDin  
Data Register  
DRDout  
DRCLK  
DRSHFT  
Altera Corporation  
August 2006  
Core Version a.b.c variable  
2–23  
MAX II Device Handbook, Volume 1  
 复制成功!