MAX II Architecture
The column interconnect operates similarly to the row interconnect. Each
column of LABs is served by a dedicated column interconnect, which
vertically routes signals to and from LABs and row and column IOEs.
These column resources include:
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■
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LUT chain interconnects within an LAB
Register chain interconnects within an LAB
C4 interconnects traversing a distance of four LABs in an up and
down direction
MAX II devices include an enhanced interconnect structure within LABs
for routing LE output to LE input connections faster using LUT chain
connections and register chain connections. The LUT chain connection
allows the combinational output of an LE to directly drive the fast input
of the LE right below it, bypassing the local interconnect. These resources
can be used as a high-speed connection for wide fan-in functions from
LE 1 to LE 10 in the same LAB. The register chain connection allows the
register output of one LE to connect directly to the register input of the
next LE in the LAB for fast shift registers. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization
and performance. Figure 2–11 shows the LUT chain and register chain
interconnects.
Altera Corporation
August 2006
Core Version a.b.c variable
2–17
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
