MAX II Architecture
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in dynamic arithmetic mode. The carry-select chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE is configured to calculate outputs for a possible carry-in of 0 and
carry-in of 1 in parallel. The carry-in0and carry-in1signals from a
lower-order bit feed forward into the higher-order bit via the parallel
carry chain and feed into both the LUT and the next portion of the carry
chain. Carry-select chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel
pre-computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delays between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the MAX II architecture
to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
Figure 2–9 shows the carry-select circuitry in an LAB for a 10-bit full
adder. One portion of the LUT generates the sum of two bits using the
input signals and the appropriate carry-in bit; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT generates
carry-out bits. An LAB-wide carry-in bit selects which chain is used for
the addition of given inputs. The carry-in signal for each chain,
carry-in0or carry-in1, selects the carry-out to carry forward to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it is fed to local, row, or column interconnects.
Altera Corporation
August 2006
Core Version a.b.c variable
2–13
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
