Logic Elements
The other two LUTs use the data1and data2signals to generate two
possible carry-out signals: one for a carry of 1 and the other for a carry of
0. The carry-in0signal acts as the carry select for the carry-out0
output and carry-in1acts as the carry select for the carry-out1
output. LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, synchronous clear, synchronous load,
and dynamic adder/subtractor options. The LAB local interconnect data
inputs generate the counter enable and synchronous up/down control
signals. The synchronous clear and synchronous load options are
LAB-wide signals that affect all registers in the LAB. The Quartus II
software automatically places any registers that are not used by the
counter into other LABs. The addnsubLAB-wide signal controls
whether the LE acts as an adder or subtractor.
Figure 2–8. LE in Dynamic Arithmetic Mode
LAB Carry-In
Carry-In0
Carry-In1
sload
sclear
aload
(LAB Wide)
(LAB Wide) (LAB Wide)
Register chain
connection
addnsub
(LAB Wide)
(1)
ALD/PRE
data1
data2
data3
LUT
ADATA
D
Row, column, and
direct link routing
Q
LUT
LUT
LUT
Row, column, and
direct link routing
ENA
CLRN
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
Local routing
LUT chain
connection
Register
chain output
Register Feedback
Carry-Out0 Carry-Out1
Note to Figure 2–8:
(1) The addnsubsignal is tied to the carry input for the first LE of a carry chain only.
2–12
Core Version a.b.c variable
Altera Corporation
August 2006
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
