Active Serial FPGA Configuration
Page 5
Figure 3 shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using the APU or a third-party programmer.
(4)
Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer (1),
V
(1)
V
(1)
V
CC
(1)
CC
CC
10 kΩ
10 kΩ
10 kΩ
Altera FPGA
CONF_DONE
nSTATUS
nCONFIG
nCEO
N.C.
EPCS Device (2)
nCE
MSEL[]
(3)
DATA
DCLK
nCS
DATA0
DCLK
nCSO
ASDO
ASDI
Notes to Figure 3:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the MSEL[]input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
In an AS configuration, the FPGA acts as the configuration master in the
configuration flow and provides the clock to the EPCS device. The FPGA enables the
EPCS device by pulling the nCSsignal low using the nCSOsignal as shown in Figure 2
and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device
using the ASDOsignal. The EPCS device responds to the instructions by sending the
configuration data to the FPGA’s DATA0pin on the falling edge of DCLK. The data is
latched into the FPGA on the next DCLKsignal’s falling edge.
1
Before the FPGA enters configuration mode, ensure that VCC of the EPCS device is
ready. If VCC is not ready, you must hold nCONFIGlow until all power rails of EPCS
device are ready.
The FPGA controls the nSTATUSand CONF_DONEpins during configuration in the AS
mode. If the CONF_DONEsignal does not go high at the end of configuration, or if the
signal goes high too early, the FPGA pulses its nSTATUSpin low to start a
reconfiguration. If the configuration is successful, the FPGA releases the CONF_DONE
pin, allowing the external 10-k resistor to pull the CONF_DONEsignal high. The FPGA
initialization begins after the CONF_DONEpin goes high. After the initialization, the
FPGA enters user mode.
f
For more information about configuring the FPGAs in AS configuration mode or
other configuration modes, refer to the configuration chapter in the appropriate
device handbook.
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
