EPCS Device Memory Access
Page 7
EPCS Device Memory Access
This section describes the memory array organization and operation codes of the
EPCS device. For the timing specifications, refer to “Timing Information” on page 29.
Memory Array Organization
Table 2 lists the memory array organization details in EPCS128, EPCS64, EPCS16,
EPCS4, and EPCS1 devices.
Table 2. Memory Array Organization in EPCS Devices
Details
EPCS128
EPCS64
EPCS16
EPCS4
EPCS1
16,777,216 bytes
(128 Mb)
8,388,608 bytes
(64 Mb)
2,097,152 bytes
(16 Mb)
524,288 bytes
(4 Mb)
131,072 bytes
(1 Mb)
Bytes
Number of sectors
Bytes per sector
Pages per sector
64
128
32
8
4
262,144 bytes
(2 Mb)
65,536 bytes
(512 Kb)
65,536 bytes
(512 Kb)
65,536 bytes
(512 Kb)
32,768 bytes
(256 Kb)
1,024
256
256
256
128
Total number of
pages
65,536
32,768
8,192
2,048
512
Bytes per page
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
Table 3 through Table 7 on page 12 list the address range for each sector in EPCS1,
EPCS4, EPCS16, EPCS64, and EPCS128 devices.
Table 3. Address Range for Sectors in EPCS1 Devices
Address Range (byte Addresses in HEX)
Sector
Start
End
3
2
1
0
H’18000
H’10000
H’08000
H’00000
H’1FFFF
H’17FFF
H’0FFFF
H’07FFF
Table 4. Address Range for Sectors in EPCS4 Devices
Address Range (Byte Addresses in HEX)
Sector
Start
End
7
6
5
4
3
2
1
0
H'70000
H'60000
H'50000
H'40000
H'30000
H'20000
H'10000
H'00000
H'7FFFF
H'6FFFF
H'5FFFF
H'4FFFF
H'3FFFF
H'2FFFF
H'1FFFF
H'0FFFF
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
