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Functional Description
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Enables the Nios processor to access unused flash memory through AS memory
interface
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Reprogrammable memory with more than 100,000 erase or program cycles
Write protection support for memory sectors using status register bits
In-system programming (ISP) support with SRunner software driver
ISP support with USB-Blaster, EthernetBlaster, or ByteBlaster II download cables
Additional programming support with the APU and programming hardware
from BP Microsystems, System General, and other vendors
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By default, the memory array is erased and the bits are set to 1
Functional Description
To configure a system using an SRAM-based device, each time you power on the
device, you must load the configuration data. The EPCS device is a flash memory
device that can store configuration data that you use for FPGA configuration purpose
after power on. You can use the EPCS device on all FPGA that support AS x1
configuration scheme.
For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the
EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from
the EPCS64 device to the EPCS128 device.
With the new data decompression feature supported, you can determine using which
EPCS device to store the configuration data for configuring your FPGA.
Example 1 shows how you can calculate the compression ratio to determine which
EPCS device is suitable for the FPGA.
Example 1. Compression Ratio Calculation
EP4SGX530 = 189,000,000 bits
EPCS128 = 134,217,728 bits
Preliminary data indicates that compression typically reduces the
configuration bitstream size by 35% to 55%. Assume worst case that is 35%
decompression.
189,000,000 bits x 0.65 = 122,850,000 bits
The EPCS128 device is suitable.
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For more information about the FPGA decompression feature, refer to the
configuration chapter in the appropriate device handbook.
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
