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Pin Information
Table 23 lists the pin description of the EPCS device.
Table 23. EPCS Device Pin Description
Pin Number Pin Number
Pin
Name
in 8-Pin
SOIC
Package
in 16-Pin
SOIC
Package
Pin Type
Description
The DATAoutput signal transfers data serially out of the EPCS device
to the FPGA during the read operation or configuration. During the
DATA
2
5
8
Output read operation or configuration, the EPCS device is enabled by pulling
the nCSsignal low. The DATAsignal transitions on the falling edge of
the DCLKsignal.
The ASDIsignal is used to transfer data serially into the EPCS device.
This pin are also receiving data that are programmed into the EPCS
device. Data is latched on the rising edge of the DCLKsignal.
ASDI
nCS
15
Input
The nCSsignal toggles at the beginning and the end of a valid
instruction. When this signal goes high, the device is deselected and
the DATApin is tri-stated. When this signal goes low, the device is
enabled and in an active mode. After power up, the EPCS device
requires a falling edge on the nCSsignal before the EPCS device
begins any operation.
1
7
Input
The FPGA provides the DCLKsignal. This signal provides the timing
for the serial interface. The data presented on the ASDIpin is latched
to the EPCS device on the rising edge of the DCLKsignal. The data on
the DATApin changes after the falling edge of the DCLKsignal and is
latched into the FPGA on the next falling edge of the DCLKsignal.
DCLK
6
16
Input
V
3, 7, 8
4
1, 2, 9
10
Power
GND
Connect the power pins to a 3.3-V power supply.
Ground pin.
CC
GND
Figure 23 shows the layout recommendation for vertical migration from the EPCS1
device to the EPCS128 device.
Figure 23. Layout Recommendation for Vertical Migration from the EPCS1 Device to the EPCS128
Device
Pin 1 ID
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
