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EP3C16F484I7N 参数 Datasheet PDF下载

EP3C16F484I7N图片预览
型号: EP3C16F484I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PBGA484, 23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL CORPORATION ]
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Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
1–7
The OCT resistance may vary with the variation of temperature and voltage after
calibration at device power-up. Use
and
to determine the final
OCT resistance considering the variations after calibration at device power-up.
lists the change percentage of the OCT resistance with voltage and
temperature.
Table 1–8. Cyclone III Devices OCT Variation After Calibration at Device Power-Up
Nominal Voltage
3.0
2.5
1.8
1.5
1.2
Equation 1–1.
dR/dT (%/°C)
0.262
0.234
0.219
0.199
0.161
dR/dV (%/mV)
–0.026
–0.039
–0.086
–0.136
–0.288
R
V
=
(V
2
– V
1
) × 1000 × dR/dV
R
T
=
(T
2
– T
1
) × dR/dT
For
R
x
< 0; MF
x
=
1/ (|R
x
|/100 + 1)
For
R
x
> 0; MF
x
=
R
x
/100 + 1
MF
=
MF
V
× MF
T
R
final
=
R
initial
× MF
Notes to
(1) T
2
is the final temperature.
(2) T
1
is the initial temperature.
(3) MF is multiplication factor.
(4) R
final
is final resistance.
(5) R
initial
is initial resistance.
(6) Subscript × refers to both
V
and
T
.
(7)
R
V
is variation of resistance with voltage.
(8)
R
T
is variation of resistance with temperature.
(9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
(10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
(11) V
2
is final voltage.
(12) V
1
is the initial voltage.
July 2012
Altera Corporation