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EP3C16F484I7N 参数 Datasheet PDF下载

EP3C16F484I7N图片预览
型号: EP3C16F484I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PBGA484, 23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL CORPORATION ]
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1–6
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Table 1–5. Cyclone III Devices Bus Hold Parameter
(Part 2 of 2)
(1)
V
CCIO
(V)
Parameter
Condition
Min
Bus-hold
low,
overdrive
current
Bus-hold
high,
overdrive
current
Bus-hold trip
point
Note to
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
1.2
Max
Min
1.5
Max
Min
1.8
Max
Min
2.5
Max
3.0
Min
Max
3.3
Min
Max
Unit
0 V < V
IN
< V
CCIO
125
175
200
300
500
500
A
0 V < V
IN
< V
CCIO
–125
–175
–200
–300
–500
–500
A
0.3
0.9
0.375 1.125
0.68
1.07
0.7
1.7
0.8
2
0.8
2
V
OCT Specifications
lists the variation of OCT without calibration across process, temperature,
and voltage.
Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description
V
CCIO
(V)
3.0
2.5
Series OCT without
calibration
1.8
1.5
1.2
Commercial
Max
±30
±30
+40
+50
+50
Industrial and Automotive
Max
±40
±40
±50
±50
±50
Unit
%
%
%
%
%
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
lists the OCT calibration accuracy at device power-up.
Table 1–7. Cyclone III Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description
V
CCIO
(V)
3.0
Series OCT with
calibration at device
power-up
2.5
1.8
1.5
1.2
Commercial Max
±10
±10
±10
±10
±10
Industrial and Automotive
Max
±10
±10
±10
±10
±10
Unit
%
%
%
%
%
July 2012 Altera Corporation