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EP3C16M164C8N 参数 Datasheet PDF下载

EP3C16M164C8N图片预览
型号: EP3C16M164C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 15408-Cell, CMOS, PBGA164, LEAD FREE, MBGA-164]
分类和应用: 可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL CORPORATION ]
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Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
1–13
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
I/O
Standard
LVDS
(Column
I/Os)
BLVDS
(Row I/Os)
(1)
(Part 2 of 2)
V
OD
(mV)
Max Min Typ
1.80
1.80 247
1.55
600
1.125 1.25 1.375
(3)
V
CCIO
(V)
Min
Typ
Max
V
ID
(mV)
Min
Max
Min
V
IcM
(V)
(2)
V
OS
(V)
Min
Typ
(3)
Condition
500 Mbps
D
MAX
700 Mbps
Max
Max
0.05 D
MAX
500 Mbps
2.375
2.5
2.625
100
0.55
1.05 D
MAX
> 700 Mbps
2.375
2.5
2.625
100
BLVDS
(Column
I/Os)
mini-LVDS
(Row I/Os)
2.375
2.5
2.625
100
2.375
2.5
2.625
300
600
1.0
1.2
1.4
mini-LVDS
(Column
I/Os)
RSDS
®
(Row
I/Os)
RSDS
(Column
I/Os)
PPDS
®
(Row I/Os)
2.375
2.5
2.625
300
600
1.0
1.2
1.4
2.375
2.5
2.625
100 200
600
0.5
1.2
1.5
2.375
2.5
2.625
100 200
600
0.5
1.2
1.5
2.375
2.5
2.625
100 200
600
0.5
1.2
1.4
PPDS
(Column
I/Os)
2.375
2.5
2.625
100 200
600
0.5
1.2
1.4
Notes to
(1) For an explanation of terms used in
refer to
in
(2) V
IN
range: 0 V
V
IN
1.85 V.
(3) R
L
range: 90
R
L
110
.
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.
(5) No fixed V
IN
, V
OD
, and V
OS
specifications for BLVDS. They are dependent on the system topology.
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.
July 2012
Altera Corporation