Stratix II Architecture
Figure 2–50. Control Signal Selection per IOE
Dedicated I/O
Clock [7..0]
io_oe
Local
Interconnect
io_sclr
Local
Interconnect
io_aclr
Local
Interconnect
io_ce_out
Local
Interconnect
io_ce_in
io_clk
Local
Interconnect
ce_out
clk_out
sclr/spreset
Local
Interconnect
clk_in
ce_in
aclr/apreset
oe
Notes to Figure 2–50:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oecan be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0]signals. The ioe_clksignals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
Altera Corporation
May 2007
2–75
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
