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EP2S130F1020I4N 参数 Datasheet PDF下载

EP2S130F1020I4N图片预览
型号: EP2S130F1020I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 6627 CLBs, 717MHz, 132540-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 时钟可编程逻辑
文件页数/大小: 248 页 / 2983 K
品牌: INTEL [ INTEL ]
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Stratix II Architecture  
Figure 2–46. Stratix II IOE Structure  
Logic Array  
OE Register  
D
Q
OE  
OE Register  
D
Q
Output Register  
D
Q
Output A  
Output B  
CLK  
Output Register  
D
Q
Input Register  
D
Q
Input A  
Input B  
Input Latch  
Input Register  
D
Q
D
Q
ENA  
The IOEs are located in I/O blocks around the periphery of the Stratix II  
device. There are up to four IOEs per row I/O block and four IOEs per  
column I/O block. The row I/O blocks drive row, column, or direct link  
interconnects. The column I/O blocks drive column interconnects.  
Figure 2–47 shows how a row I/O block connects to the logic array.  
Figure 2–48 shows how a column I/O block connects to the logic array.  
Altera Corporation  
May 2007  
2–71  
Stratix II Device Handbook, Volume 1  
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