Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.7
MLT—Master Latency Timer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
0Dh
00h
RO
8 bits
Size:
Device 0 in the (G)MCH is not a PCI master. Therefore, this register is not implemented.
Bit
Access &
Default
Description
7:0
Reserved
4.1.8
HDR—Header Type (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
0Eh
00h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Access &
Default
Description
7:0
RO
PCI Header (HDR): This field always returns 0 to indicate that the (G)MCH is a
00h
single function device with standard header layout.
4.1.9
SVID—Subsystem Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
2Ch
0000h
R/WO
16 bits
Size:
This value is used to identify the vendor of the subsystem.
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-
up to indicate the vendor of the system board. After it has been written once, it
becomes read only.
72
Datasheet
INTEL [ INTEL ]
