Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.57
LE1D—Link Entry 1 Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
150h
00000000h
RO, R/WO
32 bits
Size:
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
31:24
RO
00h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
23:16
R/WO
00h
Target Component ID: This field indicates the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:2
1
Reserved
RO
0b
Link Type: This field indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
0
R/WO
0b
Link Valid:
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
170
Datasheet
INTEL [ INTEL ]
