Networking Silicon — 82551IT
7.0
Configuration Registers
The 82551IT acts as both a master and a slave on the PCI bus. As a master, the 82551IT interacts
with the system main memory to access data for transmission or deposit received data. As a slave,
some 82551IT control structures are accessed by the host CPU to read or write information to the
on-chip registers. The CPU also provides the 82551IT with the necessary commands and pointers
that allow it to process receive and transmit data.
7.1
Function 0: LAN (Ethernet) PCI Configuration Space
The 82551IT PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured
according to its device specific configuration space. The configuration space header is depicted
below in Figure 13.
Figure 13. PCI Configuration Registers
Device ID
Status
Vendor ID
Command
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
DCh
E0h
Class Code
Revision ID
Cache Line Size
BIST
Header Type
Latency Timer
CSR Memory Mapped Base Address Register
CSR I/O Mapped Base Address Register
Flash Memory Mapped Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Reserved (PCI mode)
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address Register
Reserved
Reserved
Cap_Ptr
Max_Lat
Min_Gnt
Interrupt Pin
Next Item Ptr
Interrupt Line
Capability ID
Power Management Capabilities
Reserved Data
Power Management CSR
7.1.1
PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82551IT are both read only word entities. Their values are:
Vendor ID: 8086h
Device ID: 1209h
Datasheet
41
INTEL [ INTEL ]
