82551IT — Networking Silicon
6.1.4
100BASE-TX Link Integrity Auto-Negotiation
The 82551IT Auto-Negotiation function automatically configures the device to the technology,
media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE
specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full
duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex.
Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may
be manually configured through the MII management interface (MDI registers). Manual
configurations override the auto-select.
6.2
10BASE-T PHY Functions
6.2.1
10BASE-T Transmit Clock Generation
The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz
crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal
MAC at 2.5 MHz.
6.2.2
10BASE-T Transmit Blocks
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock
performs Manchester encoding.
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. The PHY unit supports both technologies through one pair of TD pins and by
externally sharing the same magnetics.
In 10 Mbps mode, the line drivers use a pre-distortion algorithm to improve jitter tolerance. The
line drivers reduce their drive level during the second half of “wide” Manchester pulses and
maintain a full drive level during narrow pulses and the first half of the wide pulses. This reduces
jitter caused by overcharging the line.
6.2.3
10BASE-T Receive Blocks
The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The
Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and
Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/
nibble.
In 10 Mbps mode, data is expected to be received on the receive differential pair after passing
through isolation transformers. The input differential voltage range capability for the Twisted Pair
Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer
distinguishes valid receive data, link test pulses, and idles, according to the requirements of the
10BASE-T standard.
In 10 Mbps mode, the PHY unit can detect errors in the receive data, including voltage drops prior
to the end-of-frame bit. Collision detection in 10 Mbps mode is initiated by simultaneous
transmission and reception. If the PHY unit detects this condition, it asserts a collision indication to
the CSMA/CD unit.
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Datasheet
INTEL [ INTEL ]
