Networking Silicon — 82551IT
6.0
Physical Layer Functional Description
6.1
100BASE-TX PHY Unit
6.1.1
100BASE-TX Transmit Clock Generation
A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY
unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal
Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external
crystal or oscillator must be ± 0.005% (30 ppm).
6.1.2
100BASE-TX Transmit Blocks
The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The
transmit subsection passes data unconditionally to a 4B/5B encoder.
The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5-
bit-wide parallel symbols according to the IEEE 802.3u 100BASE_TX standard. Next, the symbols
are scrambled to reduce electromagnetic emissions during long sequences of high-frequency data
codes.
The MLT-3 (multi-level signal) encoder receives the scrambled Non-Return to Zero (NRZ) data
stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-
3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are
positive, negative and zero.
The transmit differential pair line drivers are implemented with digital slope controlled current
buffers that meet the TP-PMD specifications. Current is sinked from an isolation transformer by
the TDP and TDN pins. The 125 Mbps bit stream is typically driven onto Unshielded Twisted Pair
(UTP) cable.
6.1.3
100BASE-TX Receive Blocks
The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive
differential pair. Due to the advanced digital signal processing design techniques employed, the
PHY unit will accurately receive valid data from Category 5 (CAT5) UTP cables of lengths well in
excess of 100 meters.
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the shape of the received signal. The clock recovery circuit uses
digital signal processing to compensate for various signal jitter causes. The circuit recovers the 125
MHz clock and data and presents the data to the MLT-3 decoder.
The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B
symbols originated in the transmitter. The data is decoded at the 4B/5B decoder. After the 4B
symbols are obtained, the PHY unit outputs the receive data to the CSMA unit.
In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways,
including link integrity failures, undetected start of stream delimiters, invalid symbols, or idles in
the middle of a frame.
Datasheet
35
INTEL [ INTEL ]
