82551IT — Networking Silicon
PCI_5V
2) The voltage on VIO determines the slope of the signals on the bus. Although the device
communicates if VIO is connected to 3.3V in 3.3V PCI systems, optimal performance is
acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage.
K ohm
100
All Vcc pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vcc), local bus power (Vccpl),
transmit power (Vcct), and PCI power (Vccpp) just
for clarity.
1) The decoupling
capacitor should be
added to the VIO pin.
2
1
0.1uF
G2
VIO
82551IT
AD[31:0]
AD0
N7
M7
P6
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3
L1
AD0
AD1
AD1
AD2
AD2
AD3
AD3
AD4
AD4
AD5
AD5
AD6
AD6
AD7
AD7
AD8
AD8
AD9
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
L2
K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8
P9
FLA16
3VSB
M10
FLA15/EESK
N10
FLA14/EEDO
P10
FLA13/EEDI
M11
FL A12
M12
FLA11
3VSB
EEDI
N13
3
4
2
1
FLA10
DI
CS
P13
FLA9
EEDO
EESK
N14
FLA8/IOCHRDY
M13
DO
SK
FLA7
M14
FLA6
L12
3.3K
FLA5
L13
93C46
FLA4
L14
FLA3
K14
FLA2
J12
FLA1/AUXPWR
J13
FL A0
J14
FLD7
H12
FLD6
H13
FLD5
H14
FLD4
G12
FLD3
F12
FLD2
F13
FLD1
F14
FLD0
C/BE[3:0]
EECS
C/BE0
C/BE1
C/BE2
C/BE3
P7
M4
L3
F3
C4
F2
F1
G3
H3
H1
J1
H2
J2
A2
A4
C3
J3
EECS
C/BE0#
C/BE1#
C/BE2#
C/BE3#
N9
FLCS#
N9
FLCS#
FRAME#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
M8
M9
FLOE#
FLWE#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
A13
D13
D14
D12
B12
TEST
TEXEC
TCK
INTA
INTA#
PERR#
SERR#
IDSEL
REQ#
GNT#
RST#
CLK
TI
PERR#
SERR#
IDSEL
REQ#
VREF: External VREF can be applied here if the internal reference
is not used. The internal reference is recommended, but if an
external reference is implemented, then this will cause the RBIAS
values to change.
TO
K ohm
1
C12
B14
B13
VREF
RBIAS10
RBIAS100
X1
GNT#
C2
G1
B9
A9
A6
C5
C8
RST#
1
1
2
2
RBIAS10 and RBIAS100
CLK
should be tuned for your
specific application. The
values shown are a
ISOLATE#
619
649
ISOLATE#
AUX_GOOD
PME#
ALTRS T
PME#
#
good starting value.
CLKRUN#
Pulldown resistors are used
CLKRUN#
N11
P11
on strapped pins to enable
The ISOLATE signal should be a signal that
the NAND tree test mode to
X2
is driven low just prior to the PCI bus shutting
down and it should be driven high immediately
following the PCI bus re-activation.
work. The value of 1 K ohm
B10
A10
C9
was chosen strictly on the basis
of Intel’s test fixturing requirements
Other values can be used, but it is
recommended that resistors be used
other than hard strapping the pins.
2
1
All Vss pins are connected together on the PCB
level. The power on the symbol is broken down
25 MHz
62 K ohm
between core power (Vss), local bus power (Vsspl),
transmit power (Vsst), and PCI power (Vsspp) just
for clarity.
22 pF
22 pF
PME#
To PIIX4
Figure 32. Reference Schematic Layout (Sheet 2 of 2)
96
Datasheet
INTEL [ INTEL ]
