Networking Silicon — 82551IT
3VSB
The 82551IT can drive three
LEDs with the cathode of
each device connected to
the 82551IT as shown with
the SPEEDLED or a two LED
configuration can be used,
as shown. In the two LED
configuration the link and the
activity functions share an
indicator. In this scheme the
LINK LED would flash LOW
each time activity is detected.
2
1
1
2
330
LED
330
A12
C11
B11
LILED
ACTLED
SPEEDLED
2
1
LED
This capacitor is normally not installed; however a placement can be provided.
It might need to be placed based on the results of FCC conformance testing. If it
is required, values in the pico fared range can be used. Large capacitance values
installed in this location can have a negative effect on long cable performance. So care
must be taken in selecting the values used.
8-22 pF
Keep trace length from magnetics to RJ-45 connector under one inch.
TDP C13
TDN C14
RDP E13
E14
RDN
Keep all termination resistors as
close to the 82551 as possible.
Termplane
Use plane for
this signal to
make a board
capacitor.
0.1 uF
CGND = Chassis ground
Use plane for this signal
Termplane
pF
Optional capacitor
to help with EFT
conformance.
0.1 uF
0.1 uF
82551IT
uF
Create termination plane in PCB. This plane
acts as a path for low-frequency noise that
might be coupled to unused pins. The plane
should not have any direct connection.
RECEIVE
RD+
1
7
5
6
RX+
CT
RX-
RD-
2
3
MDI-X Mode Only
7
RDC
RD+
1
RX+
1:1
TD+ 16
TD- 15
10 TX+
11 TX-
TXCT
75 Ohms
RD-
TD-
2
6
RX-
TX-
TDC 14
1:1
RECEIVE
15
11
1500pF
2kV
TRANSMIT
TD+ 16
10
TX+
1:1
TRANSMIT
MDI Mode Only
3VSB
4.7uF
4.7uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Place decoupling capacitors as close to the 82551 as possible. If component placements
are used on the bottom side of the board, then place decoupling under the 82551IT.
Figure 31. Reference Schematic Layout (Sheet 1 of 2)
Datasheet
95
INTEL [ INTEL ]
